Implementação de uma classe de códigos produto com decodificação turbo em FPGA

Abstract

Abstract This work describes a project sponsored by LINEAR Equipamentos Eletrônicos S/A and carried out at INATEL. The project aimed to implement a turbo forward error correction scheme with a low complexity block turbo codec assembled in a popular low cost FPGA. The turbo decoding is based on a combination of Pyndiah’s and Wagner's algorithms. Data rates of up to 60 Mbps were achieved using 60% of the resources in the FPGA EP1C6T144C8 produced by Altera. As a complementary result, the use of well-known and didactic simulation tools is explored, allowing the understanding of the specific class of product code and the proper FPGA implementation process. The codec was created with great flexibility using structural and behavioral models, easily translated later into the VHDL language.